The present invention relates generally to a semiconductor device and a semiconductor integrated circuit device comprising the same, and more particularly, to a semiconductor integrated circuit device having transistors which are arbitrarily connected to each other and the structure of a basic cell constituting the same.
Conventionally, in order to rapidly cope with a request from a customer, a master slice system for uniformly performing design of an LSI (Large Scale Integrated Circuit) to diffusion processing in advance, and performing only later circuit wiring for each type has been well known. The master slice system has advantages suitable for the production of few-of-a-kind LSIs, for example, shortening of a period of development and reduction of costs of development.
The semiconductor integrated circuit device of a master slice system is realized by connecting a plurality of basic cells arranged in a matrix shape or in one direction in conformity to specifications of its finished product.
For example, the structure of a general basic cell carried on a semiconductor integrated circuit device of a master slice system as described in JP-A-5-630465 is illustrated in FIG. 11.
As shown in FIG. 11, a basic cell 100 is constituted by gate electrodes 101 and 102 of a P-type MOS (Metal Oxide Semiconductor) transistor, a P-type impurity diffusion region 103 to be a drain terminal or a source terminal of the P-type MOS transistor, gate electrodes 104 and 105 of an N-type MOS transistor, an N-type impurity diffusion region 106 to be a drain terminal or a source terminal of the N-type MOS transistor, and two power supply interconnections 107 and 108.
In the semiconductor integrated circuit device of the master slice type, the plurality of basic cells 100 each having such a structure are arranged on a semiconductor substrate. The gate length L of each of the transistors in each of the basic cells 100 greatly affects the performance and the cost of the semiconductor integrated circuit device. That is, the shorter the gate length L of each of the transistors is, the higher the speed of the transistor can be made. Further, it is possible to realize a circuit on the same scale by an LSI having a small area by improving its device density.
By reducing the gate length L of each of the transistors, therefore, the semiconductor integrated circuit device is increased in scale, increased in integration density, and increased in speed. In recent years, the reduction in the gate length L of each of the transistors has progressed, for example, 0.5 xcexcM, 0.35 xcexcm, and 0.25 xcexcm. Even in the semiconductor integrated circuit device of the master slice type, the gate length L of the P-type MOS transistor and the N-type MOS transistor which are formed in each of the basic cells 100 is set to the minimum size.
As described in the foregoing, if in the semiconductor integrated circuit device of the master slice type, the basic cell having the gate length L of the minimum size is used, the semiconductor integrated circuit device can be increased in speed and increased in integration density.
If the gate length of the transistor is reduced, however, power consumption is increased by the increase in a leak current, and the effect of variations in a finning process is increased. For example, when the variations in the gate length are the same, the smaller the gate length is, the larger the ratio of the variations in the gate length to the normal gate length is, so that the larger the effect of the process variations on device characteristics is. As a result, the yield of the semiconductor integrated circuit device is reduced. There also occurs a case where margin must be provided to actual device operations in consideration of the process variations. As a result, the performance of the semiconductor integrated circuit device is reduced.
An object of the present invention is to provide a semiconductor device and a semiconductor integrated circuit device which can achieve low power consumption while achieving high speed and high integration density, and the yield and the performance of which can be prevented from being reduced by process variations.
A semiconductor integrated circuit device according to the present invention comprises a substrate, and a plurality of basic cells formed on the substrate, each of the plurality of basic cells comprising one or more transistors, the one or more transistors in at least one of the plurality of basic cells having a gate length different from that of the one or more transistors in the other basic cell.
In the semiconductor integrated circuit device, the one or more transistors in at least one of the basic cells has a gate length different from that of the one or more transistors in the other basic cell, thereby making it possible to select the basic cells depending on the necessity of operating at high speed, the necessity of reducing power consumption, and the necessity of design precision. Consequently, it is possible to construct a circuit which is operable at high speed and can be increased in integration density using the basic cell having a small gate length, and construct a circuit which can be reduced in power consumption and is hardly affected by process variations using the basic cell having a large gate length.
As a result, it is possible to achieve low power consumption while achieving high speed and high integration density as a whole, and prevent the yield and the performance from being reduced by process variations.
Each of the plurality of the basic cells may include a plurality of the transistors arranged such that they can be selectively combined with each other, and the plurality of transistors in at least one of the plurality of basic cells may have a gate length different from that of the plurality of transistors in the other basic cell.
In this case, the plurality of transistors in at least one of the basic cells has a gate length different from that of the plurality of transistors in the other basic cell, thereby making it possible to select the basic cells depending on the necessity of operating at high speed, the necessity of reducing power consumption, and the necessity of design precision. Consequently, it is possible to construct a circuit which is operable at high speed and can be increased in integration density using the basic cell having a small gate length, and construct a circuit which can be reduced in power consumption and is hardly affected by process variations using the basic cell having a large gate length.
As a result, it is possible to achieve low power consumption while achieving high speed and high integration density, and prevent the yield and the performance from being reduced by process variations.
At least one of the plurality of transistors may have a gate length different from that of the other transistors in each of the basic cells.
In this case, the transistors can be selected depending on the necessity of operating at high speed, the necessity of reducing power consumption, and the necessity of design precision in each of the basic cells. Consequently, it is possible to construct a circuit which is operable at high speed and can be increased in integration density by connecting the transistors having a small gate length in each of the basic cells, and construct a circuit which can be reduced in power consumption and is hardly affected by process variations by connecting the transistors having a large gate length.
As a result, it is possible to achieve low power consumption while achieving high speed and high integration density for each of the basic cells as a whole, and prevent the yield and the performance from being reduced by process variations.
At least one of the plurality of transistors may be arranged in a direction different from the direction in which the other transistors are arranged in each of the basic cells.
In this case, at least one of the transistors is arranged in the direction different from the direction in which the other transistors are arranged, so that the degree of freedom in the direction of line connection is increased.
The one or more transistors in each of the basic cells may include one or a plurality of transistors of a first conductivity type and one or a plurality of transistors of a second conductivity type, the one or a plurality of transistors of the first conductivity type and the one or a plurality of transistors of the second conductivity type being arranged such that they can be selectively combined with each other, and the one or a plurality of transistors of the first conductivity type and the one or a plurality of transistors of the second conductivity type in at least one of the plurality of basic cells may have a gate length different from that of the one or a plurality of transistors of the first conductivity type and the one or a plurality of transistors of the second conductivity type in the other basic cell.
In this case, the one or more transistors of the first conductivity type and the one or more transistors of the second conductivity type in at least one of the basic cells have a gate length different from that of the one or more transistors of the first conductivity type and the one or more transistors of the second conductivity type in the other basic cell, thereby making it possible to select the basic cells depending on the necessity of operating at high speed, the necessity of reducing power consumption, and the necessity of design precision. Consequently, it is possible to construct a circuit which is operable at high speed and can be increased in integration density using the basic cell having a small gate length, and construct a circuit which can be reduced in power consumption and is hardly affected by process variations using the basic cell having a large gate length.
As a result, it is possible to achieve low power consumption while achieving high speed and high integration density as a whole, and prevent the yield and the performance from being reduced by process variations.
The one or more transistors in each of the basic cells may include one or a plurality of transistor pairs each comprising a transistor of a first conductivity type and a transistor of a second conductivity type, the one or a plurality of transistor pairs being arranged such that they can be selectively combined with each other, the transistor of the first conductivity type and the transistor of the second conductivity type in each of the transistor pairs may share a gate electrode, and the gate electrode of each of the one or a plurality of transistor pairs in at least one of the plurality of basic cells may have a gate length different from that of the gate electrode of each of the one or a plurality of transistor pairs in the other basic cell.
In this case, a gate electrode of each of the one or more transistor pairs in at least one of the basic cells has a gate length different from that of a gate electrode of each of the one or more transistors in the other basic cell, thereby making it possible to select the basic cell depending on the necessity of operating at high speed, the necessity of reducing power consumption, and the necessity of design precision. Consequently, it is possible to construct a circuit which is operable at high speed and can be increased in integration density using the basic cell having a small gate length, and construct a circuit which can be reduced in power consumption and is hardly affected by process variations using the basic cell having a large gate length.
As a result, it is possible to achieve lower power consumption while achieving high speed and high integration density, and prevent the yield and the performance from being reduced by process variations.
The one or more transistors in each of the basic cells may comprise a gate electrode having a wide portion at its center or end.
In this case, it is possible to increase the degree of freedom in line connection and shorten interconnections utilizing the wide portion provided at the center or the end of the gate electrode of the one or more transistors.
Each of the basic cells may further comprise an interconnection line provided in a space among the one or more transistors.
In this case, it is possible to increase the degree of freedom of line connection and shorten the interconnections by utilizing the interconnection line provided in the space.
Each of the basic cells may be formed in a cell region in a square shape, and further comprise a power supply line provided along at least one side of the cell region.
In this case, it is possible to connect the transistors to the power supply line while minimizing the intersection of the interconnections.
The plurality of transistors or the plurality of transistor pairs may be arranged such that they can be selectively combined with each other in each of the basic cells.
In this case, the basic cells are selected depending on the necessity of operating at high speed, the necessity of reducing power consumption and the necessity of design precision, thereby making it possible to construct a circuit which is operable at high speed and can be increased in integration density using the plurality of transistors or the plurality of transistor pairs in the basic cell having a small gate length, and construct a circuit which can be reduced in power consumption and is hardly affected by process variations using the plurality of transistors or the plurality of transistor pairs in the basic cell having a large gate length.
As a result, it is possible to achieve lower power consumption while achieving high speed and high integration density as a whole, and prevent the yield and the performance from being reduced by process variations.
A semiconductor integrated circuit device according to another aspect of the present invention comprises a substrate, one or a plurality of first basic cells formed on the substrate, and one or a plurality of second basic cells formed on the substrate, the first basic cell comprising one or more transistors arranged such that they can be selectively combined with each other and having a first gate length, the second basic cell comprising one or more transistors arranged such that they can be selectively combined with each other and having a second gate length larger than the first gate length, the one or more transistors in at least one of the one or a plurality of first basic cells being connected to each other, to construct a first circuit which is operable at high speed, the one or more transistors in at least one of the one or a plurality of second basic cells being connected to each other, to construct a second circuit which is operable with low power consumption and operable with high precision.
In the semiconductor integrated circuit device, it is possible to construct the first circuit which is operable at high speed by connecting the one or more transistors having the first gate length in at least one of the first basic cells, and construct the second circuit which can be reduced in power consumption and operable with high precision by connecting the one or more transistors having the second gate length in at least one of the second basic cells.
In this case, the first circuit is constituted by the one or more transistors having a small gate length, so that the occupied area is reduced. The second circuit is constituted by the one or more transistors having a large gate length, so that it is hardly affected by process variations.
Consequently, it is possible to achieve low power consumption while achieving high speed and high integration density as a whole and prevent the yield and the performance from being reduced by process variations.
A semiconductor integrated circuit device according to still another aspect of the present invention comprises a substrate, and a plurality of basic cells formed on the substrate, each of the basic cells comprising a plurality of transistors arranged such that they can be selectively combined with each other, and at least one of the plurality of transistors having a gate length different from that of the other transistors in at least one of the basic cells.
In the semiconductor integrated circuit device, at least one of the transistors in at least one of the basic cells has a gate length different from that of the other transistors, thereby making it possible to select the transistors depending on the necessity of operating at high speed, the necessity of reducing power consumption, and the necessity of design precision. Consequently, it is possible to construct a circuit which is operable at high speed and can be increased in integration density by connecting the transistors having a small gate length, and construct a circuit which can be reduced in power consumption and is hardly affected by process variations by connecting the transistors having a large gate length.
As a result, it is possible to achieve lower power consumption while achieving high speed and high integration density, and prevent the yield and the performance from being reduced by process variations.
At least one of the plurality of transistors may be arranged in a direction different from the direction in which the other transistors are arranged in each of the basic cells.
In this case, at least one of the transistors is arranged in the direction different from the direction in which the other transistors are arranged, so that the degree of freedom in the direction of line connection is increased.
A semiconductor device according to a further aspect of the present invention comprises a substrate, and a plurality of transistors arranged such that they can be selectively combined with each other on the substrate, at least one of the plurality of transistors having a gate length different from that of the other transistors.
In the semiconductor device, at least one of the transistors has a gate length different from that of the other transistors, thereby making it possible to select the transistors depending on the necessity of operating at high speed, the necessity of reducing power consumption, and the necessity of design precision. Consequently, it is possible to construct a circuit which is operable at high speed and can be increased in integration density by connecting the transistors having a small gate length, and construct a circuit which can be reduced in power consumption and is hardly affected by process variations by connecting the transistors having a large gate length.
Consequently, the semiconductor device according to the present invention is used as a basic cell, thereby making it possible to realize a semiconductor integrated circuit device which can achieve lower power consumption while achieving high speed and high integration density as a whole, and the yield and the performance of which can be prevented from being reduced by process variations.
The plurality of transistors may include one or a plurality of transistors of a first conductivity type and one or a plurality of transistors of a second conductivity type, the one or a plurality of transistors of the first conductivity type and the one or a plurality of transistors of the second conductivity type may be arranged such that they can be selectively combined with each other.
In this case, at least one of the transistors has a gate length different from that of the other transistors, thereby making it possible to select the transistors of the first conductivity type and the transistors of the second conductivity type depending on the necessity of operating at high speed, the necessity of reducing power consumption, and the necessity of design precision. Consequently, it is possible to construct a circuit which is operable at high speed and can be increased in integration density by connecting the transistors having a small gate length, and construct a circuit which can be reduced in power consumption and is hardly affected by process variations by connecting the transistors having a large gate length.
Consequently, the semiconductor device according to the present invention is used as a basic cell, thereby making it possible to realize a semiconductor integrated circuit device which can achieve low power consumption while achieving high speed and high integration density as a whole, and the yield and the performance of which can be prevented from being reduced by process variations.
The plurality of transistors may include a plurality of transistor pairs each comprising a transistor of a first conductivity type and a transistor of a second conductivity type, the plurality of transistor pairs being arranged such that they can be selectively combined with each other, the transistor of the first conductivity type and the transistor of the second conductivity type in each of the transistor pairs may share a gate electrode, and the gate electrode of at least one of the plurality of transistor pairs may have a gate length different from the gate electrode of the other transistor pair.
In this case, the gate electrode of at least one of the transistor pairs has a gate length different from the gate electrode of the other transistor pair, thereby making it possible to select the transistor pairs depending on the necessity of operating at high speed, the necessity of reducing power consumption, and the necessity of design precision. Accordingly, it is possible to construct a circuit which is operable at high speed and can be increased in integration density by connecting the transistor pairs having a small gate length, and construct a circuit which can be reduced in power consumption and is hardly affected by process variations by connecting the transistor pairs having a large gate length.
Consequently, the semiconductor device according to the present invention is used as a basic cell, thereby making it possible to realize a semiconductor integrated circuit device which can achieve low power consumption while achieving high speed and high integration density as a whole, and the yield and the performance of which can be prevented from being reduced by process variations.
The plurality of transistors may include a plurality of transistors having a first gate length and a plurality of transistors having a second gate length larger than the first gate length, the plurality of transistors having the first gate length may be connected to each other, to construct a first circuit which is operable at high speed, and the plurality of transistors having the second gate length may be connected to each other, to construct a second circuit which is operable with low power consumption and operable with high precision.
In this case, the first circuit which is operable at high speed is constructed by connecting the plurality of transistors having the first gate length, and the second circuit which is operable with low power consumption and operable with high precision by connecting the plurality of transistors having the second gate length. In this case, the first circuit is constituted by the plurality of transistors having a small gate length, so that the occupied area is reduced. Further, the second circuit is constituted by the plurality of transistors having a large gate length, so that it is hardly affected by process variations.
Consequently, the semiconductor device according to the present invention is used as a basic cell, thereby making it possible to realize a semiconductor integrated circuit device which can achieve low power consumption while achieving high speed and high integration density as a whole, and the yield and the performance of which can be prevented from being reduced by process variations.
At least one of the plurality of transistors may be arranged in a direction different from the direction in which the other transistors are arranged.
In this case, at least one of the transistors is arranged in the direction different from the direction in which the other transistors are arranged, so that the degree of freedom in the direction of line connection is increased.
The semiconductor device may further comprise an interconnection line provided in a space among the plurality of transistors on the substrate.
In this case, the interconnection line provided in the space among the plurality of transistors is utilized, thereby making it possible to increase the degree of freedom in line connection and shorten the interconnections.
The plurality of transistors may be arranged in a cell region in a square shape, and the semiconductor device may further comprise a power supply line provided along at least one side of the cell region.
In this case, it is possible to connect the transistors to the power supply line while minimizing the intersection of the interconnections.
Each of the plurality of transistors may comprise a gate electrode having a wide portion at its center or end.
In this case, the wide portion provided at the center or the end of the gate electrode of the plurality of transistors is utilized, thereby making it possible to increase the degree of freedom in line connection and shorten the interconnections.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.